1. Filed of the Invention
The present invention refers to a method of producing a trench insulation in a substrate.
2. Description of the Related Art
In the prior art, limits are set to the application of integrated semiconductor circuits, especially CMOS circuits, on a monocrystalline silicon basic material, so-called bulk silicon, wafers with regard to the use at high ambient temperatures. When power components are used, application limits result from the dissipation power of the component, which causes an increase in the crystal temperature during operation. The maximum dielectric strength that can be achieved is then limited by the blocking property of the pn junctions and by the so-called latch-up effect.
The cause of these limitations is essentially to be found in the fact that, in conventional circuits, the components defining the circuit are electrically insulated from one another by blocked pn doped junctions. This has the effect that, on the one hand, a voltage limit is given by the breakdown voltage of these pn junctions and, on the other hand, the circuit design is subjected to restrictions insofar as pn junctions block only in one voltage direction, but conduct the current in the inverted voltage direction. The limitation of the maximum admissible crystal temperature of these components is additionally given by the surrounding volume of the crystal material which is large in comparison with the volume of the actual component, e.g. the transistor. From a temperature of 130xc2x0 C. onwards, the undesired transistor leakage current caused by the crystal temperature is no longer predominantly due to the generation of electron hole pairs in the space-charge zones of the blocked pn junctions themselves, but it is predominantly due to those electron hole pairs which are generated in the vicinity of the pn junction, diffuse to said pn junction and contribute to the reverse current.
In the prior art, it is known that these limitations can be partly or fully eliminated by introducing a dielectric insulation instead of the insulation by means of pn junctions; in the case of such a dielectric insulation, each of the individual components defining the integrated circuit is fully surrounded by an insulator.
This kind of insulation is known in the prior art, but its production normally entails great expenditure.
For this purpose, so-called Silicon On Insulator silicon wafers (SOI silicon wafers; SOI=Silicon On Insulator) are commercially available; when these silicon wafers are used for producing integrated circuits, a dielectric insulation from the basic material is given. In this case, the basic material only serves as a mechanical support.
The lateral dielectric insulation can be achieved e.g. by the so-called mesa technique, but with the drawback of great topographic height differences after the mesa etching. This topology is not tolerable within modern VLSI and ULSI processes (VLSI=Very Large Scale Integration; ULSI=Ultra Large Scale Integration) and, without additional levelling measures, it is therefore incompatible.
For solving the problem of lateral dielectric insulation, the so-called trench insulation technique has therefore become generally accepted in the prior art. This technique comprises the step of etching a trench into the monocrystalline usable semiconductor layer at the smallest possible distance permitted by the technical-physical boundary conditions, said trench extending from the wafer surface to the boundary of the monocrystalline usable semiconductor layer. The trench surrounds the individual components or groups of individual components in the form of a closed boundary. For eliminating the differences in height resulting from trench etching and for achieving a permanent insulating property, it is necessary to fill the trench with an electrically insulating material, or to coat the trench walls with an electrically insulating material and to fill the residual trench with semi-insulating, semiconductor or conductive material.
The materials that can be used for this purpose are only those which are compatible with the subsequent semiconductor-technological production steps. The methods used are e.g. complete filling of the trench by thermal oxidation, partial filling of the trench by thermally oxidizing the trench walls and additional filling of the rest of the trench e.g. by means of a silicon dioxide, doped silicon dioxide, polysilicon or amorphous silicon, which are all deposited by means of a conformingly depositing CVD process (CVD=Chemical Vapour Deposition=chemical deposition from the vapour phase). If the material deposited is insulating, also said material alone can be used for filling the trench. Normally, an anisotropic back-etching step will be necessary after the CVD process.
The above-described methods of producing a trench insulation show a plurality of disadvantages. These disadvantages are
that process control is complicated,
that individual process steps must be used, which demand a great deal from the equipment used and from the settings of the devices used,
that the demands with regard to process tolerances are high,
that indiviudal process steps are used, which are not compatible with the demands to be met in the case of a CMOS production process,
that a plurality of additional lithographic steps is required,
that high demands are to be met with regard to the adjusting accuracy of successive masking steps,
that, in addition to the standard CMOS process steps to be carried out, the further steps required for producing the trench must be carried out with a high additional expenditure, and
that a large amount of lateral space is required for the insulation.
EP 0 656 651 A2 refers to a method of producing an integrated circuit arrangement, comprising the step of producing, in a two-step trench process, a trench structure in a substrate wafer. In a first etching step, a trench mask is produced, and, in a second etching step, the trench structure in the substrate wafer is produced. Subsequently, the trench structure is filled by whole-area deposition of an amorphous silicon layer, whereby silicon spacers are formed. Following this, SiO2 spacers are formed by oxidation of the silicon spacers and the remaining space between the spacers is filled with a silicon filling which is produced by oxidation so as to close the trench structure by a cover. Filling of the trench is not effected by a local oxidation technique. WO 93/10559 refers to a method of producing deep trenches in semiconductor substrates, which are filled with insulation material. A trench is etched in an appropriately prepared substrate, the walls of the trench being then lined with a dielectric material in a subsequent step. Following this, a thick polysilicon layer is deposited onto the whole substrate, whereby also the trench is filled with the polysilicon. It follows that the trench is not filled by a local oxidation technique.
Starting from this prior art, it is the object of the present invention to provide a method of producing a trench insulation in a silicon wafer, which guarantees simple process control and which carries out a plurality of necessary sub-process steps, without any additional expenditure, together with the standard CMOS process steps that have to be carried out anyway.
The present invention provides a method of producing a trench insulation in a silicon wafer. The method has the steps of depositing a first silicon-oxide layer on a ore manufactured sequence of layers on the front surface of a silicon wafer, structuring the first silicon-oxide layer so as to define a mask for a subsequent production of a trench, etching a trench having a predetermined depth in the silicon wafer making use of said mask, filling the trench with a silicon oxide, conforming deposition of a first polysilicon layer on the first silicon-oxide layer and on the oxide-filled trench, removing the first polysilicon layer in such a way that a polysilicon cover remains on said oxide-filled trench and removing the first silicon-oxide layer.
In comparison with the prior art described hereinbefore, the present invention provides a plurality of advantages, viz.
that process control is simple;
that individual process steps are used, which demand as little as possible from the equipment, said process steps permitting thus the production of a trench insulation in a manner which is as simple as possible and simultaneously reliable,
that individual process steps are used, which demand as little as possible from the setting of the machines,
that the demands to be met by the process tolerances are as low as possible (large process windows),
that indiviudal process steps are used, which are compatible with the demands to be met in the case of a CMOS production process,
that only a single additional lithographic step is required,
that no unusually high demands are to be met by the adjusting accuracy of successive masking steps and that constrained mask derivatives are not necessary,
that the temporal succession of the additional steps which are specific to trench production is chosen such that subtasks are automatically carried out, without any additional expenditure, together with standard CMOS process steps which are to be carried out anyhow,
that little lateral space is required for the insulation,
that future advantages in comparison with known methods can be seen, when in the course of the foreseeable technical development the lithographic dimensions used in production will be reduced still further.